An important stage in the fabrication of semiconductor devices is ensuring that a device is behaving as designed. This stage, known as “test,” is often performed using automatic test equipment, or “testers,” which analyze the behavior of the device automatically. Such automatic test equipment comprise complex electronics capable of sending test signals to, and measuring values of test signals from, one or more test points on one or more devices under test (DUTs).
For many types of tests, a tester needs to generate and/or measure test signals at a rate that corresponds to the rate at which the DUT is operating. Otherwise, there would be cycles of DUT operation in which no stimulus is provided to the DUT, which could cause incorrect operation of the DUT. Alternatively, there could be cycles of DUT operation in which the tester does not measure values at the DUT such that the tester may not detect incorrect operation of the DUT. Therefore, in order to test modern, high speed semiconductor devices, the tester must generate and measure test signals at a very fast rate.
The challenge of controlling test signal operations at a high rate is complicated by the fact that the tester may need to perform multiple operations to generate or measure test signals for each cycle of DUT operation. For some tests, the operations performed in the tester to generate or measure a test signal are defined by a test pattern. In operation, circuitry inside the tester, called a “pattern generator,” may execute the pattern. The pattern generator must execute the test pattern at a rate that allows the tester to generate and measure test signals at a rate that ensures there are test signals for every cycle of DUT operation.
The test pattern may specify, for each of numerous tester cycles, what signals to send to, or that are expected to be measured at, each of numerous test points on the DUT. These tester cycles may be the same as or faster than the cycles of DUT operation such that tester operations are specified for every cycle of DUT operation.
A test pattern contains a sequence of vectors, each of which specifies the operation of channel circuitry that can generate or measure a test signal for one cycle of the tester's operation. In addition, a vector may contain information that specifies a subsequent vector to be executed. In some instances, the information in a vector may indicate that the next vector to be executed is stored in a memory at a location following the vector being executed. Execution in this way is said to be sequential. However, in other instances, this information in a vector specifying the next vector to be executed may specify a non-sequential location such that execution of the test pattern “branches.” In some instances, these branches may be conditional branches such that the order in which vectors in a test pattern that are executed may be dynamically determined based on the observed responses from the DUT or on other conditions that the tester hardware is constructed to identify.
Conditional branches increase the challenge of quickly executing a test pattern. In a conventional microprocessor, fast execution of program instructions can be achieved through a pipelined architecture. With a pipelined architecture, circuitry to perform an instruction is divided into pieces, which are called ranks. The ranks are separated by registers or other data storage components such that when processing within one rank is completed, the result may be stored in a register until the next rank is ready to process it. The circuitry within a pipeline can be controlled so that, when a rank in the pipeline is processing a portion of one instruction, the preceding rank is processing a portion of the next sequential instruction.
Circuitry within each rank likely can complete processing on a portion of an instruction faster than circuitry configured to perform the entire instruction. As a result, pipelined circuitry can process a sequence of instructions at a faster rate than non-pipelined circuitry.
A tradeoff of this faster rate of processing of sequential operations is that there is latency between when the pipeline begins to execute an instruction and when results of that processing are first available. Because each rank in the pipeline needs to wait for the preceding rank to generate an output before it can begin processing for an instruction, the pipeline does not produce an output for the first instruction in a sequence until each rank has processed that operation such that the time to the first result is the sum of processing delays in all of the ranks. Thereafter, the pipelined circuitry can produce outputs at a rate set by the longest processing time in a single rank.
This additional delay when a sequence of instructions is first provided for processing creates a disruption in output of the pipelined circuitry if a new sequence of instructions is supplied for execution. Such a disruption occurs when a conditional branch instruction is executed. A branch defines a new starting point for a sequence of instructions to be processed. Because it is not known whether the branch will be taken until after the conditional branch instruction is executed, a new sequence of operations cannot be applied to the pipeline until a result of executing the conditional branch instruction is available. Thus, no output of the pipeline is supplied if the branch is taken until after that delay associated with restarting.
The pipeline is said to be “stalled” during this delay. In a conventional microprocessor, the delay associated with a stalled pipeline is on average offset by the faster rate at which instructions can be executed after the stall. However, in a tester such a disruption in processing vectors in a test pattern is undesirable because there could be cycles of DUT operation during which processing is stalled, creating the possibility that input is not supplied to the DUT or a result is not measured at the appropriate time, impacting results of a test.
To allow faster execution without impacting the results of a test, some testers are designed with very fast circuitry such that, even if multiple tester cycles are required to execute a vector, execution may be completed within one cycle of DUT operation. However, such high speed circuitry may be expensive. Alternatively, some testers may be designed to execute test patterns with a limited amount of conditional branching. However, such an approach limits functionality of the tester.